1. Field of the Invention
The present invention is related to a method for predicting cycle time; in particular, to a method of predicting cycle time required for completing a wafer fabrication process.
2. Description of Related Art
In semiconductor manufacturing, each lot of wafers must undergo multiple fabrication processes in order to create the final required semiconductor components. In order to increase operational margins, semiconductor manufacturers have been making every possible effort to reduce the fabrication time required for each lot of wafers, facilitating augmentation of overall yields in semiconductor fabrication plants.
However, many factors influence the time needed for completing the entire semiconductor fabrication process. In addition to the time required for a wafer to undergo each fabrication process, an other essential factor is the time spent by each lot of wafers while waiting for being processed.
The time required for each lot of wafers to complete one fabrication process plus the time spent waiting until reaching the subsequent fabrication process is referred as cycle time. After a specific lot of wafers has undergone the fabrication process, then getting ready to start the next fabrication process, engineers need to determine to which machine tool the lot of wafers is going to be distributed for the next fabrication process. Engineers decide such a distribution of wafers based on their work experience, theoretical knowledge, current load in each machine tool as well as other important factors, with a view to make the queue lots in each machine tool (i.e. number of lots of wafers queuing for entering into the machine tool; for example, the number of lots of wafers in a machine tool is 3, indicating there are three lots of wafers queuing to enter into the machine tool for process) as small as possible.
However, since engineers can not be aware beforehand when the wafers in the forward fabrication process will arrive; that is, the cycle time of the forward fabrication process for a certain lot of wafers is unknown. As a result, engineers may only first wait and expect passively the arrival of the wafers, then start to consider the issue of distribution to which machine tool for the lot of wafers; therefore, appropriate planning in advance for wafer distribution during the fabrication process is very difficult.
Sometimes several lots of wafers may arrive at the same time; in this case, if engineers decide the distribution in haste, uneven distribution may occur, causing many lots of wafers to be collectively distributed to the same machine tool; whereas, suppose engineers over-prudently consider the distribution, many lots of wafers may be delayed and remain in idle. No matter which condition might occur, waiting time for wafer process would be prolonged, thus further affecting the overall yield of the semiconductor factory.
Consequently, if the cycle time of a forward fabrication process can be precisely predicted and appreciated by engineers in advance, it would be helpful for engineers to schedule the following fabrication process beforehand.
Accordingly, the inventors of the present invention have considered the aforementioned disadvantages and proposed the present invention of reasonable design which is able to effectively improve the disadvantages.